The present invention relates to a receiver circuit, an interface circuit, and an electronic instrument.
In recent years, a high-speed serial transfer interface such as low voltage differential signaling (LVDS) has attracted attention as an interface standard aiming at reducing EMI noise or the like. In the high-speed serial transfer interface, data transfer is realized by allowing a transmitter circuit to transmit serialized data using differential signals and a receiver circuit to differentially amplify the differential signals. Japanese Patent Application Laid-open No. 2002-314397 has disclosed a conventional technology relating to the high-speed serial transfer interface, for example.
However, since the high-speed serial transfer interface allows current to constantly flow through the transmitter circuit and the receiver circuit, a reduction of power consumption is limited. On the other hand, data transfer cannot be performed if the path of the constant current is cut. Therefore, the technical subject is to realize setting and cancellation of a power-down mode in the transmitter circuit and the receiver circuit conforming to the high-speed serial transfer interface.